1. Field of the Invention
The present invention generally relates to integrated circuit manufacturing processes and, more particularly, to processes for forming robust conductive structures on advanced insulating materials.
2. Description of the Prior Art
Increases in both performance and manufacturing economy with increased integration density have led to the use of design rules with extremely small feature sizes and closeness of spacing in integrated circuit design. Reduced interconnection length between devices included in integrated circuits generally reduces signal propagation time and increases noise immunity. However, as integrated circuits are scaled to smaller design rules, reductions in wiring delays are diminished by increases in resistance (due to decreased cross-sectional area) and capacitance (due to increased connection proximity). This effect can only be ameliorated by reduced resistivity of conductors and/or dielectric constant of insulators. Accordingly, advanced dielectric materials having low dielectric constants have been developed and used in manufacture of integrated circuits.
Among such advanced materials having particularly low dielectric constants now in widespread use are some silsesquioxane materials (hereinafter SSQ) which are particularly preferred for their ease of application, much in the nature of conventionally applied spin-on glass and gap filling qualities. The filling of gaps is important to reduce likelihood of propagation of crystal lattice dislocations and cracks in semiconductor materials which may carry significant internal stresses.
Suitable SSQ materials are commercially available polymer materials, one of which is principally, if not entirely, hydrogen silsesquioxane (HSiO.sub.3/2), sometimes referred by the acronym HSSQ or HSQ. A related material sometimes employed is methyl silsesquioxane (MSSQ or MSQ) in which a methyl group is substituted for the hydrogen in HSQ. These materials form a structure in which bridging oxygen atoms are shared between molecules. While the dielectric constant is low, the bridging oxygen atoms are strained and can be attacked by numerous chemicals or result in rapidly propagating cracks from relatively minor physical damage. For that reason, unprotected SSQ materials are not generally considered suitable for formation of layers even though they exhibit good planarizing characteristics that would support high resolution lithographic processes. For example, U.S. Pat. No. 5,818,111 notes the relative fragility of HSQ and proposes a structure of alternating layers of HSQ and protective silicon dioxide to form a multi-layer dielectric stack.
Damascene processing, alluded to above, is a well-understood and mature technology which is particularly useful for mechanically forming robust connections of superior electrical integrity at very small sizes and close spacings. Basically, a Damascene process defines the desired shape of conductors by the formation of a groove or recess in the surface of a dielectric material followed by deposition of a layer of metal of sufficient thickness to fill the recesses. The layer of metal is then readily patterned by planarization to the original surface of the dielectric by any known process such as polishing. The structure so formed fully supports the metal at the bottom and sides of a connection (which may be made of materials such as gold, aluminum, tungsten or copper) and thus is resistant to metal migration, damage or the like. The formation of the groove or recess can also generally be formed with greater precision and regularity of the edges of the pattern than can be achieved by direct patterning of the layer of metal.
When forming conductors on a dielectric layer above a substantially completed chip, however, two patterning processes are required for formation of the interconnect patterns and for forming connections to devices on the chip in the form of vias alluded to above, respectively. These two patterning processes followed by metal deposition and planarization are collectively referred to as a dual Damascene process.
However, most SSQ materials are readily attacked by most lithographic resist developers which are generally of high pH. Moreover, when the SSQ material is attacked by resist developers, the amount of material which may be removed is not readily controllable and may undercut the resist pattern. Thus, when the SSQ is etched, even with a well-controlled etchant, the resulting via shape may be quite distorted and vias will lack uniformity across the chip and possibly be irregularly and unreliably registered with the structures on the chip to which the vias are to form connections.
Protection of the surface of the SSQ material with a further layer of material such as another dielectric is not practical in some semiconductor structures such as formation of connection vias in a dual Damascene process. Virtually any otherwise suitable material for protection of an SSQ material would have a dielectric constant which is higher than that of SSQ and even a very thin layer would increase capacitance at a location where capacitance may be critical and may possibly require a different etchant and/or an additional etching process to remove in accordance with a resist pattern. Additionally, while a protective layer may be deposited on an original surface of an SSQ layer deposition of a protective layer in an etched feature (e.g. in a trench or groove) would require additional process steps as well as compromising the low capacitance of any conductive structure formed therein for which the SSQ material was employed.
Of course, the concept of using a resist is predicated on the assumption that the underlying material will not be affected by the processing and development of the resist until the resist pattern is fully formed. Since the SSQ material removal by the resist developer appears to be a function of the breaking of fragile shared oxygen bonds, it is unlikely that a developer could be found which would not attack the SSQ material. Accordingly, at the present state of the art, processes using multiple resist layers would provide no significant benefit toward reduction of the problem.
In summary, use of HSQ or MSQ to underlie or support interconnection metallization allows use of dual Damascene processes to produce conductors and vias only with the likelihood that manufacturing yield will be compromised. While SSQ materials can be used as a gap fill material over connections applied to a surface, the advantages of damascene connections noted above are not achieved thereby. No technique has been available for avoiding the basic incompatibility of SSQ materials and resist developers in processes requiring a sequence of patterned etch steps, such as in a dual damascene process, particularly for accommodating fine pitch design rules for high density integrated circuits where the low dielectric constant of SSQ materials is particularly critical.